1. Field of the Invention
This invention relates to a sense circuit especially used as a sense amplifier for amplifying a very small voltage difference read out of a memory cell in a semiconductor memory device.
2. Description of the Related Art
A prior art sense amplifier circuit is shown in FIG. 8. This sense circuit is well known as CMOS current mirror type sense amplifier. It comprises P-channel type MOS FETs Q1 and Q2 constituting a current mirror circuit, N-channel type differential input MOS FETs Q3 and Q4, and an N-channel type MOS FET Q5 functioning as a current source. The MOS FET Q1 has a source, which is connected to a power source terminal 11 which is applied with a power source voltage Vcc. The gate and drain of MOSFET Q1 are commonly connected with a drain of the MOS FET Q3. The MOS FET Q2 has a source which is connected with the power source terminal 11. The gate of MOSFET Q2 is connected with the gate of the MOS FET Q1, and its drain is connected with a drain of the MOS FET Q4 and an output terminal 12. The MOS FET Q3 has a gate which is connected with an input terminal 13-1, and its source is connected with a source of the MOS FET Q4. A gate of the MOS FET Q4 is connected with an input terminal 13-2. The input terminals 13-1 and 13-2 are supplied with differential input signals. The source of MOS FET Q3 is coupled to the source of MOS FET Q4. A MOS FET Q5 is coupled between the sources of MOS FETs Q3 and Q4 and ground. The conductance of MOS FET Q5 is controlled by a sense circuit activation signal SA. Note that the conductance ratio between the MOS FETs Q1 and Q3 is set to be equal to that between the MOS FETs Q2 and Q4.
Now, the operation of the above structured sense amplifier will be explained below. When the sense circuit activation signal SA is in a high level (a higher voltage than a threshold voltage of the MOS FET Q5), the MOS FET Q5 is rendered conductive and the sense circuit is set in an activated state. When the sense circuit activation signal SA is in a low level (a lower voltage than the threshold voltage of the MOS FET Q5), the sense circuit is set in a non-activated state. Therefore, when the voltage of the input terminals 13-1 and 13-2 is set higher than the threshold voltage of the MOS FETs Q3 through Q5 while the signal SA is in a high level, the MOS FETs Q1, Q3 and Q5 are rendered conductive. Thus, a bias current flows between the source and drain of the MOS FET Q1 and the drain of the MOS FET Q1 or the gate of the MOS FET Q2 is biased to an intermediate voltage. The voltage of the output terminal 12 will be equal to the gate bias voltage of the MOS FET Q2 when the voltage of the input terminal 13-2 is equal to that of the input terminal 13-1, because the conductance ratio between the MOS FETs Q2 and Q4 is set to be equal to that between the MOS FETs Q1 and Q3. The voltage of the output terminal 12 will be lower than the gate bias voltage of the MOS FET Q2 when the voltage of the input terminal 13-2 is higher than that of the input terminal 13-1, whereas the voltage of the output terminal 12 will be higher than the gate bias voltage of the MOS FET Q2 when the voltage of the input terminal 13-2 is lower than that of the input terminal 13-1.
FIG. 9 shows another embodiment of a conventional sense circuit. This circuit has the same circuit structure as that shown in FIG. 8 with an additional N-channel type MOS FET Q6, whose drain and source are connected between the source common connection point of the MOS FETs Q3 and Q4 and the drain of the MOS FET Q5. The gate of the MOS FET Q6 is connected with the gate common connection point of the MOS FETs Q1 and Q2
Due to the above structure, the gate of the MOS FET Q2 is biased to an intermediate voltage as stated above, and the gate of the MOS FET Q6 is applied with the intermediate voltage. Therefore, the MOS FET Q6 functions as a pentode, so that the same current characteristics can be obtained irrespective of the fluctuation of the differential input signals supplied to the input terminals 13-1 and 13-2. Therefore, the current supply capacity can be made constant, and thus provides improved operational stability as compared with the circuit shown in FIG. 8.
However, the circuits shown in FIG. 8 and FIG. 9 consume power very much since a substantially constant bias current always flows in the activated state. To reduce the power consumption, the capacity to drive the load connected with the output terminal 12 will be lowered, which is a drawback.